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— An Interview with Prof. Kamakoti, IITM

Building India’s Processor Ecosystem
— An Interview with Prof. Kamakoti, IITM

Prof. Kamakoti


Prof. Kamakoti of Indian Institute of Technology Madras is leading India’s first successful attempt in developing a comprehensive range of processor families from tiny IoT class processors to server grade cores. Prof. Kamakoti’s dream of making an indigenous processor for India under Project Shakti, will reach critical milestone in April 2019 with the release of a server class chip using RISC V ISA. With this, IIT-M will be among the handful of institutions worldwide to have created a complete open source microprocessor ecosystem. Prof. Kamakoti was awarded the ACCS-CDAC Foundation Award 2018 along with Prof. Vijay Kumar of Indian Institute of Science. Prashanth Hebbar from ACC Journal caught up with Prof. Kamakoti on his work. This is an excerpt from the interview.

Stanford, MIT and now IIT Madras have developed new processor ecosystems based on RISC V? Are we heading towards an industry which is more fragmented than ever? How do you characterize this new push towards RSIC V based processor ecosystems?

Today, when we look at the use of processors, there is a significant difference between what happened in the past and what is happening currently. One distinguishing mark between the previous century and this century is that the use of processors in different application domains has spread quite widely. Today, I use processors in washing machines, intelligent locks, surveillance cameras, agriculture, healthcare, physical fitness gadgets, public utility services, finance, POS machines, electronic voting machines and so on. I can keep on going.

The main issue here is heterogeneity. If I talk just about IoT, the IoT that goes in a car is different from the IoT that goes in a smart glass. There is a lot of heterogeneity that comes up when you basically start looking at the kind of ways in which I am going to use technology. Which means, I may not be able to have one single processor [architecture] which may effectively and efficiently solve all the problems. That’s why the 2018 Turing Award winners, John Hennessy and David Patterson, rightly said that you must look at domain specific [processor] architectures.

Customization of processors is the need of the day and open source will enable that customization and facilitate certain ecosystem which will make it economically viable.

In your paper on Shakti, you talked about the virtues of instruction set extensibility? Why is it important?

The domain specificity is what is going to be the success of this new era. The ability to add small hardware here and a small bit there to suit a particular use case, is facilitated by the instruction set architecture. So, extensibility of the instruction set architecture becomes crucial using which we can quickly add the extra instruction needed. We can also very quickly touch the software stack and make the compiler use new hardware we added. If the compiler doesn’t use the system, then the hardware we added remains a waste.

That brings us to the questions of how efficient our compilers are? Do you see a problem there? How does RISC V and its extensible instruction set help here?

Traditionally, there has been a big disconnect between compiler and the [processor] architecture. Take some of the old complex instruction set architectures which offer a lot of architectural features, but very rarely will the compiler even compile the code to [optimum levels] because compilers are fine tuned for a general impact.

The processor architecture companies have a huge compiler presence and they essentially fine tuning the compiler to a generalized impact but if someone attempts to fine tune further, they may not gain much – usually 3–4% gain is what is achieved in such cases. I did my computer architecture assignment in 1992 under Professor Kalyan Krishnan (IIT Madras). We took a 32-bit C compiler to understand how much of the 32-bit features of the architecture is being used. We found out that only five percent of the total addressing words were being utilized and 95% silicon was just lying there. This situation hasn’t improved much in recent times.

These are some of the issues for effective functioning in special purpose hardware. If I am going to look at IoT where I have power restrictions, area restrictions, form factor, memory restrictions and so on, I need a lot of optimization.

In this context, RISC V ushers in an interesting paradigm. Let us take a simple example. Today, many of the processors only set a flag when a divide by zero error occurs and do not automatically take you to an exception handler. That is handled by the compiler. Now, if you look at some of the safety critical applications, divide by zero is a nightmare and they must be handled right. Suppose, I need to make a processor for that type of safety critical application, using commercially off the shelf processors may just not be an answer. These kinds of issues are only the tip of the iceberg.

We are told that by 2022, there will be 50 billion IoT devices. Let us even say 10% of it is true, that itself is a huge volume. Important to note is that these IoT devices are not gigahertz applications, they are megahertz applications and today many of these applications can even be run on an FPGA and structured ASIC. If you just take the FPGA and make a chip, it will be five times faster on one fifth the power.

What do you think is the tipping point of your work? What makes it different from other efforts across the world?

For anyone to quickly make a processor and get it deployed is not easy. All said and done, with 12 students everything being new, we have been through two successful tape-outs. Both are running Linux, all the things that we wanted to port have been ported and it’s working fine.

What stands out is that now we have an ecosystem wherein people can quickly take a processor, customize it to whatever their needs are, make applications, port their software, run it. All these things can be done on small Rs 5,000 FPGA boards. When satisfied, they can run volumes like in millions and can go for an ASIC. For smaller volumes, like 10,000 volumes, they make a smaller investment and make a structured ASIC and so on.

This ecosystem now exists which is going to drive the real economic sense to what it means to make a processor.


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