Binary to Reverse Converter
With these blocks now we are ready regarding FIR filter computation provided input residues are given. The input residues corresponding to given input binary words can be easily obtained for the various moduli as follows: The residue mod 2n for a 3n-bit number is n least significant bits itself. The residue mod (2n-1) can be obtained by adding the three n –bit words in the given 3n-bit number. Considering the given number as X = a.22n+b.2n+c, we have residue mod (2n-1) as r2 = (a+b+c) mod (2n-1).
As explained before, we can add the three words in a CSA followed by a CPA with EAC. In the case of modulus (2n+1), we find (a-b+c) mod (2n+1). We add a and c with two’s complement of b and the result if negative, we add 2n+1. If the result is positive, we subtract 2n+1. As an illustration, suppose we consider moduli 16, 15 and 17 and given 12 bit word is 1001,0100,11002, we compute r1, r2 and r3 as r1 = 12, r2 = (9+4+12) mod 15 = 10 and r3 = (9-4+12) mod 17 = 0. The reader may verify this to be true since input given decimal number is 2380.
FIR filter implementation
We will next describe a 64 tap FIR filter implementation using the example from Jenkins and Leon  whose coefficients are given in Table. The coefficients are scaled to get the integer part. The filter takes 64 input samples and weighs them using the tap weights given in Table I and finds the sum. We need to estimate the worst case maximum of the sum of product of coefficients and all samples to be of maximum value say 8 bits with one sign bit as 2784×128 = 356,352 corresponding to 18.44 bits. This dynamic range (DR) can be met by choosing for example four moduli as 15, 16, 17 and 31. The DR achievable is 2,127,840 (> 20 bits). Thus, we need four Binary to RNS converters, 4 RNS accumulators (mod mi adders), 4 RNS multipliers and finally one RNS to Binary converter. The computation time is ΔFC+ 64ΔMAC+ ΔRC. The one of the reverse converters described in literature can be used. Alternatively, a three moduli RNS can be used with moduli 127,128 and 129 yielding DR of 21 bits. One needs to assess the total area requirements and largest MAC time and decide on the choice of moduli set. Note that since we have considered worst case dynamic range, no need for scaling arises.
Table I. Coefficients of FIR filter
Using small building blocks such as Modulo adders, subtractors, multipliers, efficient processors for custom VLSI DSP applications can be designed. It has been shown in literature that the use of RNS can lead to low power designs as well. Of late, several applications in cryptography have benefited from the use of RNS to crunch extremely large numbers. We have considered the design of FIR filters but the techniques described can be extended to IIR filters as well.